Title :
Very Low-Complexity Hardware Interleaver for Turbo Decoding
Author :
Wang, Zhongfeng ; Li, Qingwei
Author_Institution :
Oregon State Univ., Corvallis
fDate :
7/1/2007 12:00:00 AM
Abstract :
This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs.
Keywords :
broadband networks; code division multiple access; interleaved codes; turbo codes; VLSI architectures; computation complexity; hardware interleaver; turbo decoding; turbo interleave pattern generation unit; wideband CDMA systems; Circuits; Computer architecture; Computer science; Decoding; Delay; Digital signal processing; Hardware; Multiaccess communication; Turbo codes; Very large scale integration; CDMA; VLSI architecture; interleaver; turbo codes;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2007.895313
