DocumentCode
1056468
Title
Endurance of thin-oxide nonvolatile MNOS memory transistors
Author
White, Marvin H. ; Dzimianski, John W. ; Peckerar, Martin C.
Author_Institution
Westinghouse Electric Corporation, Baltimore, MD
Volume
24
Issue
5
fYear
1977
fDate
5/1/1977 12:00:00 AM
Firstpage
577
Lastpage
580
Abstract
A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2 interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si3 N4 dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 1010erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time.
Keywords
Conductivity; Control systems; Dielectrics; Digital signal processing; Helium; Interface states; Nonvolatile memory; Silicon; Transistors; Tunneling;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1977.18781
Filename
1478973
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