A symmetrically balanced linear differential charge-splitting input for charge-coupled devices

A new charge input scheme for charge-coupled devices is described. Charge packets of a fixed size are produced in each clock cycle. Each charge packet is subsequently split into two parts under two input gates. The difference between the two resulting fractional charge packets is a linear function of the potential difference between the two signal input gates. This input scheme is particularly suitable for use with differential charge-coupled delay lines, since the charge representation of the input signal and its complement are produced in a highly symmetrical manner. The principle may also be used for splitting charge packets in any required ratio for more general application.