Ultrafast pipelined arithmetic using quantum electronic devices

Author

Mohan, S. ; Mazumder, P. ; Haddad, G.I.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

141

Issue

2

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

104

Lastpage

110

Abstract

Negative differential resistance characteristics of several new quantum electronic devices have been used to design high-speed logic gates with the latching property. These latching gates form the basis of the ultrafast pipelined adder circuit described in this paper. The latching or memory feature of these circuits, which was previously considered to be a nuisance in the design of combinational circuits, is exploited to overcome the pipeline overheads of area and time. Simulation studies show that application of pipelining techniques can provide an effective throughput of one 32-bit addition every 1.6 ns using minimal hardware

Keywords

combinatorial circuits; digital arithmetic; flip-flops; integrated circuits; logic gates; negative resistance; pipeline processing; semiconductor devices; 1.6 ns; 32 bit; adder circuit; area overhead; combinational circuits; high-speed logic gates; latching gates; memory feature; negative differential resistance characteristics; pipeline overheads; quantum electronic devices; simulation studies; throughput; time overhead; ultrafast pipelined arithmetic;

fLanguage

English

Journal_Title

Computers and Digital Techniques, IEE Proceedings -

Publisher

iet

ISSN

1350-2387

Type

jour

DOI

10.1049/ip-cdt:19941000

Filename

278051