A 300-MHz BiCMOS serial data transceiver

Author

Thompson, Barry ; Lee, Hae-Seung ; DeVito, L.M.

Author_Institution

MIT, Cambridge, MA, USA

Volume

29

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

185

Lastpage

192

Abstract

A BiCMOS circuit for serial data communication is presented. The chip has phase-locked loops for transmit frequency synthesis and receive clock recovery, serial-to-parallel and parallel-to-serial converters, and encode and decode functions. Since this is a mixed-analog/digital design, and the transmitter and receiver operate asynchronously, many techniques are used to decrease noise coupling. A 1.2 μm BiCMOS process allows operation at speeds of 300 MHz along with this high level of system integration, and the chip consumes less than 1 W from a single 5 V supply

Keywords

BiCMOS integrated circuits; data communication equipment; data conversion; decoding; encoding; mixed analogue-digital integrated circuits; phase-locked loops; semiconductor device noise; transceivers; 1 W; 1.2 micron; 300 MHz; 5 V; BiCMOS circuit; PLL; asynchronous operation; mixed-analog/digital design; noise coupling reduction; parallel-to-serial converters; phase-locked loops; receive clock recovery; serial data communication; serial data transceiver; serial-to-parallel converters; single 5 V supply; transmit frequency synthesis; BiCMOS integrated circuits; Circuit synthesis; Clocks; Data communication; Decoding; Frequency conversion; Frequency locked loops; Frequency synthesizers; Phase locked loops; Transceivers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.278339

Filename

278339