Special applications of the voting model for bridging faults

Author

Millman, Steven D. ; Acken, John M.

Author_Institution

Motorola Inc., Tempe, AZ, USA

Volume

29

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

263

Lastpage

270

Abstract

A transistor-level examination of bridging faults and the resulting logic-level bridging fault model is described. Experiments with simulations and silicon demonstrate its accuracy. Previous work has demonstrated the accuracy and efficiency of the voting model for bridging faults. This paper presents a complete formal description of the voting model. In addition, simple solutions to special applications of the voting model which generalize its applicability are presented. These applications include the Byzantine General´s Problem, complex gate designs, and nonuniform transistor sizes. How to use Binary Decision Diagrams to compare the voting model to other fault models is also presented. Finally, delay tests are shown to be a poor means for detecting bridging faults. This work was done to show that the voting model, a logic-level model for bridging faults, accurately describes the behavior of real faults in real circuits

Keywords

CMOS integrated circuits; delays; fault location; integrated circuit testing; integrated logic circuits; logic testing; Byzantine General´s Problem; CMOS digital circuits; binary decision diagrams; bridging faults; complex gate designs; delay tests; fault model; formal description; logic-level model; nonuniform transistor sizes; transistor-level examination; voting model; CMOS logic circuits; Circuit faults; Circuit testing; Data structures; Electrical fault detection; Fault detection; Fault diagnosis; Silicon; Voltage; Voting;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.278347

Filename

278347