Abstract :
Shrinking feature sizes and GHz clock rates are undermining the life expectancy of mainstream semiconductor devices. The high current densities and voltage gradients associated with design rules of 130 nm and below could erode metal connections and oxide insulation layers, leading to a dramatic reduction in the expected operating life of silicon chips. There are three main silicon chip wear-out mechanisms: electromigration, oxide breakdown, and hot-carrier interaction. This paper examines the problems raised by chip wear-out and various means to combat them. Special emphasis is place on safety critical applications and those that require an extended operational component life.
Keywords :
current density; electromigration; hot carriers; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; nanoelectronics; safety; semiconductor device breakdown; 130 nm; chip wear-out mechanisms; electromigration; feature size shrinking; high clock rates; high current densities; high voltage gradients; hot-carrier interaction; metal connection erosion; nanometer-scale IC life expectancy; nanoscale design rules; oxide breakdown; oxide insulation layer erosion; safety critical applications;
