DocumentCode :
1058449
Title :
Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits
Author :
Almukhaizim, Sobeeh ; Shi, Feng ; Love, Eric ; Makris, Yiorgos
Author_Institution :
Dept. of Comput. Eng., Kuwait Univ., Safat
Volume :
17
Issue :
7
fYear :
2009
fDate :
7/1/2009 12:00:00 AM
Firstpage :
869
Lastpage :
882
Abstract :
We discuss the problem of soft errors in asynchronous burst-mode machines (ABMMs), and we propose two solutions. The first solution is an error tolerance approach, which leverages the inherent functionality of Muller C-elements, along with a variant of duplication, to suppress all transient errors. The proposed method is more robust and less expensive than the typical triple modular redundancy error tolerance method and often even less expensive than previously proposed concurrent error detection methods, which only provide detection but no correction. The second solution is an error mitigation approach, which leverages a newly devised soft-error susceptibility assessment method for ABMMs, along with partial duplication, to suppress a carefully chosen subset of transient errors. Three progressively more powerful options for partial duplication select among individual gates, complete state/output logic cones, or partial state/output logic cones and enable efficient exploration of the tradeoff between the achieved soft-error susceptibility reduction and the incurred area overhead. Furthermore, a gate-decomposition method is developed to leverage the additional soft-error susceptibility reduction opportunities arising during conversion of a two-level ABMM implementation into a multilevel one. Extensive experimental results on benchmark ABMMs assess the effectiveness of the proposed methods in reducing soft-error susceptibility, and their impact on area, performance, and offline testability.
Keywords :
asynchronous circuits; error correction codes; Muller C-elements; asynchronous burst-mode circuits; benchmark ABMMs; complete state-output logic cones; error mitigation approach; gate-decomposition method; partial state-output logic cones; soft-error susceptibility assessment method; soft-error tolerance; Asynchronous burst-mode circuits; soft errors; soft-error mitigation; soft-error susceptibility; soft-error tolerance;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2014381
Filename :
5067005
Link To Document :
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