DocumentCode :
1058457
Title :
Innovative structures for CMOS combinational gates synthesis
Author :
Buonanno, Giacomo ; Sciuto, Donatella ; Stefanelli, Renato
Author_Institution :
Dipartimento di Elettronica, Politecnico di Milano, Italy
Volume :
43
Issue :
4
fYear :
1994
fDate :
4/1/1994 12:00:00 AM
Firstpage :
385
Lastpage :
399
Abstract :
Design of multiple outputs CMOS combinational gates is studied. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. The two techniques can be combined together to obtain further area reductions. Different synthesis algorithms are discussed, from exhaustive enumeration to branch and bound to heuristic techniques allowing to speed up the synthesis process. Simulation results for synthesis are introduced to compare the different algorithms. Design examples are also provided. Electrical simulations show that the dynamic behavior of such structures is comparable to the traditional static or domino implementations (obviously the new and traditional structures have the same static behavior)
Keywords :
CMOS integrated circuits; combinatorial circuits; logic design; logic gates; minimisation of switching nets; CMOS combinational gates; CMOS gates; Combinatorial gates; Delta networks; Lambda networks; area minimization; branch and bound; combinational gates synthesis; delay analysis; exhaustive enumeration; heuristic techniques; logic synthesis; multiple outputs functions; synthesis algorithms; transistor interconnection structures; CMOS logic circuits; Circuit synthesis; Delay; Design optimization; Integrated circuit interconnections; Logic gates; Minimization methods; Network synthesis; Programmable logic arrays; Variable structure systems;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.278478
Filename :
278478
Link To Document :
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