DocumentCode :
1058467
Title :
Reliable floating-point arithmetic algorithms for error-coded operands
Author :
Lo, Jien-Chung
Author_Institution :
Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
Volume :
43
Issue :
4
fYear :
1994
fDate :
4/1/1994 12:00:00 AM
Firstpage :
400
Lastpage :
412
Abstract :
Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers
Keywords :
digital arithmetic; error correction codes; redundancy; Berger check prediction; Berger encoded; computer arithmetic; concurrent error detection; error-coded operands; floating-point arithmetic; hardware redundancy; high-density VLSI; low-cost residue codes; redundancy ratios; reliable floating-point multiplication; residue encoded; soft-errors; standard IEEE floating-point numbers,; Application software; Code standards; Computer errors; Digital arithmetic; Equations; Floating-point arithmetic; Hardware; Redundancy; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.278479
Filename :
278479
Link To Document :
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