DocumentCode
1058554
Title
A Microprocessor for Speech Recognition
Author
Kawakami, Yuichi ; Ishizuka, Hisao ; Watari, Masao ; Sakoe, Hiroaki ; Hoshi, Toshiaki ; Iwata, Toshiki
Author_Institution
NEC Corporation, Kawasaki, Japan
Volume
3
Issue
2
fYear
1985
fDate
3/1/1985 12:00:00 AM
Firstpage
369
Lastpage
376
Abstract
A new single-chip microprocessor for speech recognition, the SRP, has been developed, utilizing a multiprocessor architecture and a pipelined structure. It can recognize up to 340 isolated words or 40 connected words in real time. The SRP contains a vector distance calculator, a DP-equation calculator, and an I/O controller operating in a pipelined manner. Algorithm variations and operation parameters are user programmable, and the total size of the SRP program for a typical speech recognition system is about 700 words. The device has been fabricated with n-channel Si-gate E/D MOS technology with 2.5 μm design rules and employs 7296 three-transistor dynamic RAM cells for a total of more than 40 000 transistors.
Keywords
Speech recognition; DRAM chips; Hardware; MOSFETs; Microprocessors; Out of order; Pattern recognition; Speech analysis; Speech recognition; User interfaces; Vocabulary;
fLanguage
English
Journal_Title
Selected Areas in Communications, IEEE Journal on
Publisher
ieee
ISSN
0733-8716
Type
jour
DOI
10.1109/JSAC.1985.1146207
Filename
1146207
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