Comments on "Area-time optimal adder design"

Author

Chien-In Henry Chen ; Kumar, Ajit

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

Volume

43

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

507

Lastpage

512

Abstract

A previous paper by Wei and Thompson (1990) defined a family of adders based on a modular design and presented an excellent systematic method of implementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with respect to area and time. The authors first explicitly demonstrate the optimal 32-bit fast carry generator, described by Wei and Thompson, is incorrect. With suitable corrections, a correct 32-bit fast carry generator design is then presented. Next, BiCMOS technology is applied to implement the subcircuit of fast carry generator to accelerate the critical path. The authors show that the critical path delay of 16-bit, 32-bit and 66-bit adders is respectively shortened to 83.89%, 86.89% and 90.62% after introducing the BiCMOS drivers.<>

Keywords

adders; carry logic; BiCMOS drivers; VLSI parallel adder; critical path delay; fast carry generator; optimal 32-bit fast carry generator; optimal adder design; Adders; BiCMOS integrated circuits; CMOS technology; Computer errors; Delay; Design optimization; Difference equations; Dynamic programming; MOS devices; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.278491

Filename

278491