The Hi-C RAM cell concept

This paper addresses a new MOS high-capacity dynamic RAM cell concept called the high capacity (Hi-C) RAM cell. This cell combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DP) structure, and its operation is identical to that of conventional dynamic RAM cells. A charge-capacity analysis was undertaken which indicates that the Hi-C cell has a charge storage capacity per unit area 50-100 percent greater than that of the regular 1-T or DP cells. It is also expected to have a leakage current lower than that of the 1-T and DP cells. Results of measurements on the first test structures show a 45-80-percent increase in charge capacity and up to 3× reduction in leakage current. In addition, the implant doses can be conveniently chosen so that the charge capacity of the Hi-C cell is maximized and independent of the n-type implant dose in the storage region. This is important regarding manufacturability. This new cell structure represents a significant breakthrough in increased charge capacity and decreased leakage current which should very favorably impact dynamic RAM packing density.