DocumentCode :
1060059
Title :
Selective ion implantation to reduce power consumption in MOS integrated circuits
Author :
Ahmed, H. ; Charpentier, A.
Author_Institution :
Cambridge University, Cambridge, England
Volume :
25
Issue :
5
fYear :
1978
fDate :
5/1/1978 12:00:00 AM
Firstpage :
547
Lastpage :
548
Abstract :
A method of using implantation to reduce 
in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.
in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.Keywords :
Circuit testing; Energy consumption; Implants; Impurities; Integrated circuit technology; Ion implantation; Large scale integration; MOS integrated circuits; MOSFETs; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1978.19128
Filename :
1479522
Link To Document :
