DocumentCode :
1060717
Title :
The flame fusion technique: Present state of the art at the material, device, and circuit levels
Author :
Borel, Joseph ; Trilhe, Jacques ; Ricard, Jean
Author_Institution :
Laboratoire D´´Electronique et de Technologie de L´´Informatique, Grenoble Cedex, France
Volume :
25
Issue :
8
fYear :
1978
fDate :
8/1/1978 12:00:00 AM
Firstpage :
864
Lastpage :
868
Abstract :
One of the present limitations of silicon-on-sapphire (SOS) technology is the cost of the starting material. It has been proved that this technology allows to build circuits with higher operating frequencies and denser than bulk technology. These advantages would be increased thanks to a lowering of substrate cost. One of the solutions is to use the flame fusion (FF) technique to replace Czochralski (CZ) growing of crystals. We deserve in this paper the present state of the art of the flame fusion growth of sapphire. This technique allows a significant decrease in material cost. We have evaluated a 50-percent decrease in cost at the 3-in "ingot" level (compared to CZ ingot cost1) for production levels of 100 000 wafers per year (the quality of the deposited silicon epi-layer seen through CMOS test circuits being the same). This cost saving is mainly due to: 1) absence of crucible in FF growth, 2) lower cost of furnaces, 3) lower cost of raw material. As the material cost accounts for nearly 50 percent of the cost of the sapphire substrate, we can expect a 25-percent saving at the sapphire substrate level when using FF growth instead of CZ growth. We describe the results obtained on material growth (on 2- and 3-in wafers), substrate characterization, and test of devices and circuits.
Keywords :
Circuit testing; Costs; Crystalline materials; Crystals; Fires; Frequency; Furnaces; Production; Raw materials; Silicon;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1978.19192
Filename :
1479586
Link To Document :
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