Threshold voltage model of ESFI-SOS-MOS transistors

A threshold voltage model for ESFI-SOS transistors is presented accounting for the thin-film structure and the existence of the silicon-sapphire interface. The model uses simplifying assumptions in order to obtain analytical expressions. In most practical cases the charge at the silicon-sapphire interface is sufficiently high to accomplish a saturation effect of the value of the threshold voltage. Consequently, the exact value of the interface charge must not be known in order to calculate the value of the threshold voltage; the sign of the interface charge, however, has a drastic effect. Experimental results are in good agreement with calculated values. The threshold voltage can be reproducibly controlled to the extent that the ESFI-SOS technique can be utilized for low-voltage applications as well.