Title :
Compact NOI Nanodevice Simulation
Author_Institution :
Dept. of Microelectron., Politeh. Univ. of Bucharest, Bucharest, Romania
Abstract :
The nothing-on-insulator (NOI) transistor was recently proposed and is based on the conduction through a vacuum nanocavity. The main contributions of this brief are: 1) the NOI device study on alternative materials and 2) New key device parameters. The simulations reveal optimum NOI structure with 15-nm film thicknesses, possessing a subthreshold drain slope of 50 mV/dec, ION/IOFF ratio of 1012, and a switching time under 0.3 ps. Although the NOI device is related to the tunnel or vacuum device as phenomena, it distinctly evolves toward a compact nanostructure, with the main advantage of nanometric sizes on all three directions, becoming interesting for very large-scale integration systems.
Keywords :
VLSI; field effect transistors; semiconductor device models; NOI transistor; compact NOI nanodevice simulation; compact nanostructure; key device parameters; nothing-on-insulator transistor; optimum NOI structure; size 15 nm; subthreshold drain slope; tunnel device; vacuum device; vacuum nanocavity; very large-scale integration systems; Electric breakdown; Logic gates; Performance evaluation; Silicon; Tunneling; Very large scale integration; Field Effect Transistors; semiconductors devices; tunneling; tunneling.;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2013.2278474
