Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing

We introduce the 32 nm SOI Boeing Interleaved Flip-Flop, which is based on the DICE topology with additional RHBD layout enhancements. Sensitive node pairs were separated by interleaving elements of the flip-flop cell, to attain the required SEU performance while minimizing the area, speed and power impact. The Boeing Interleaved Flip-Flop takes advantage of the reduced charge sharing inherent to an SOI technology to maintain a two order of magnitude SEU improvement relative to the unhardened flip-flop, which corresponds to more than an order of magnitude SEU rate reduction compared to our 90 nm DICE.