Through-Silicon-Via Fabrication Technologies, Passives Extraction, and Electrical Modeling for 3-D Integration/Packaging

Major advances have been made in the processing technologies of through-silicon-vias (TSVs) because TSV is an essential element for both wafer-level 3-D integration and packaging-based 3-D integration, due to its short interconnect length, high interconnect density, and small footprint. Based on a review of current TSV technologies, this paper reports a number of recently developed extraction techniques to investigate TSV parasitics using a 3-D fullwave electromagnetic (EM) simulator, a SPICE simulator, and empirical calculations. All the TSV RLGC values extracted from the fullwave simulation are in good agreement with those from different approaches over the entire frequency range of interest. The proposed empirical calculations indicate close results to fullwave extraction, thus TSV can be accurately modeled as lump elements. A wideband SPICE model for circuit design is generated from the TSV EM solution with good matching for both magnitudes and phases of return loss and insertion loss. Sensitivity analysis results further indicate that the insulating layer thickness weighs most in signal gain at 20 GHz. As an application of the modeling approaches is developed, a novel coaxial TSV with superior electrical performance is proposed, and its latency and power are examined. This paper provides some insight into TSV electrical characteristics and physical design to maximize the benefits of 3-D systems.