DocumentCode :
1063497
Title :
A 64 kbit MOS dynamic random access memory
Author :
Natori, Kenji ; Ogura, Mitsugi ; Iwai, Hiroshi ; Maeguchi, Kenji ; Taguchi, Shinya
Author_Institution :
Toshiba Corporation, Kawasaki, Japan
Volume :
26
Issue :
4
fYear :
1979
fDate :
4/1/1979 12:00:00 AM
Firstpage :
560
Lastpage :
563
Abstract :
A 
bit dynamic random access memory is developed using 4 µm design rules, a 320-Å thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.
bit dynamic random access memory is developed using 4 µm design rules, a 320-Å thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.Keywords :
Circuits; DRAM chips; Extrapolation; Fabrication; Helium; History; Lithography; Random access memory; Read-write memory; Research and development;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1979.19460
Filename :
1480038
Link To Document :
