DocumentCode
1064081
Title
N-step incremental straight-line algorithms
Author
Gill, Graeme W.
Author_Institution
Labtam Australia Pty. Ltd., Mordialloc, Vic., Australia
Volume
14
Issue
3
fYear
1994
fDate
5/1/1994 12:00:00 AM
Firstpage
66
Lastpage
72
Abstract
This class of algorithms extends Bresenham´s (1965) integer straight-line algorithm to generate more than one pixel per inner loop, thus reducing inner loop overhead. The quad-step algorithm is too large to justify its use in older hardware with limited memory space, but it can be viable in the context of modern memory and software sizes. Because the algorithm reduces both calculation overhead and the number of memory accesses for adjacent pixels, it can improve the performance of current systems that are limited in their processor speed and of future systems that might be limited in their memory speed. The algorithm gives results identical to those from Bresenham´s single-step routine while drawing pixels in the expected direction from start to end point. Furthermore, as the gradual trend towards more bits per pixel continues, a processor supporting multi-word burst data instructions could make good use of this algorithm in speeding up line drawing into a 24-bits-per-pixel, 1-pixel-per-word color frame buffer. I chose to implement 4 steps per loop because it gave a useful performance improvement without exceeding the resources of the target processor, and it was small enough to hand-code. However, the techniques described can be used to construct a straight-line algorithm that generates more than 4 steps per loop. The relatively small average decision tree sizes indicate that algorithms of greater than 4 pixels per step might further improve line-drawing efficiency.<>
Keywords
computer graphics; N-step incremental straight-line algorithms; adjacent pixels; calculation overhead; color frame buffer; decision tree sizes; hand-coding; inner loop overhead; integer straight-line algorithm; line drawing efficiency; memory accesses; memory speed; multi-word burst data instructions; performance improvement; processor speed; quad-step algorithm; Acceleration; Arithmetic; Australia; Computer displays; Computer graphics; Counting circuits; Equations; Microprocessors; Reduced instruction set computing; Testing;
fLanguage
English
Journal_Title
Computer Graphics and Applications, IEEE
Publisher
ieee
ISSN
0272-1716
Type
jour
DOI
10.1109/38.279047
Filename
279047
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