• DocumentCode
    106446
  • Title

    Analysis of static and dynamic performance of organic inverter circuits based on dual and single gate organic thin film transistors

  • Author

    Goswami, V. ; Kumar, Bijendra ; Kaushik, B.K. ; Yadav, K.L. ; Negi, Yuvraj Singh

  • Author_Institution
    Dept. of Phys., Indian Inst. of Technol. Roorkee, Roorkee, India
  • Volume
    7
  • Issue
    6
  • fYear
    2013
  • fDate
    Nov-13
  • Firstpage
    345
  • Lastpage
    351
  • Abstract
    In this study, electrical behaviour of dual-gate (DG) and single-gate (SG) organic thin film transistors (OTFTs) is investigated using Atlas two-dimensional (2D) numerical device simulation. Compared with the SG, DG organic transistor shows improved performance because of the presence of two channels formed in DG device by charge carrier modulation. Furthermore, this study introduces all-p organic inverter circuits with diode-load and zero-Vgs-load logic configurations using SG and DG structures. Static and dynamic behaviour of all-p organic inverter circuits is compared with addressing the effect of both the devices. A maximum voltage gain (AV) of 16 is obtained in zero-Vgs-load logic using DG-OTFT, whereas SG-OTFT configuration produces a maximum AV of about 6.27. Significant improvements in propagation delay of 66% for diode-load and 53% for zero-Vgs-load logic using DG-OTFT are obtained as compared with SG-OTFT.
  • Keywords
    logic circuits; logic gates; numerical analysis; organic field effect transistors; thin film transistors; 2D numerical device simulation; Atlas two-dimensional numerical device simulation; DG device; DG organic transistor; DG-OTFT configuration; SG organic transistor; SG-OTFT configuration; all-p organic inverter circuits; charge carrier modulation; diode-load; dual gate organic thin film transistors; dynamic behaviour; dynamic performance analysis; electrical behaviour; organic inverter circuits; propagation delay; single gate organic thin film transistors; static behaviour; static performance analysis; zero-voltage-load logic;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices & Systems, IET
  • Publisher
    iet
  • ISSN
    1751-858X
  • Type

    jour

  • DOI
    10.1049/iet-cds.2013.0044
  • Filename
    6673763