DocumentCode :
1065175
Title :
An automated design tool for analog layouts
Author :
Zhang, Lihong ; Kleine, Ulrich ; Jiang, Yingtao
Author_Institution :
Dept. of Electr. & Inf. Eng., Magdeburg Univ. of Technol.
Volume :
14
Issue :
8
fYear :
2006
Firstpage :
881
Lastpage :
894
Abstract :
In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices, our layout generation tool attempts to optimize more complex modules. This tool includes a complete tool suite that covers the following three major analog physical designs stages. 1) Module Generation: designers can develop and maintain their own technology- and application-independent module generators for subcircuits using an in-house developed description language. 2) Placement: a two-stage placement technique, tailored for the analog placement design, is proposed. In particular, this placement algorithm features a novel genetic placement stage followed by a fast simulated reannealing scheme. 3) Routing: the minimum-Steiner-tree-based global routing is developed, and it is actually integrated into the placement procedure to improve reliability and routability of the placement solutions. Following the global routing, a compaction-based constructive detailed routing finally completes the interconnection of the entire layout. Several testing circuits have been applied to demonstrate the design efficiency and the effectiveness of this tool. Experimental results show that this new layout tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time
Keywords :
electronic engineering computing; integrated circuit layout; network routing; simulated annealing; trees (mathematics); analog circuit layouts; analog integrated circuits; analog layouts; analog placement design; application-independent module generators; automated design tool; compaction-based constructive detailed routing; description language; fast simulated reannealing scheme; genetic placement stage; layout generation tool; layout synthesis tool; minimum-Steiner-tree-based global routing; module generation; Analog circuits; Analog integrated circuits; Circuit simulation; Circuit synthesis; Circuit testing; Design automation; Genetics; Integrated circuit reliability; Integrated circuit synthesis; Routing; Algorithms; analog integrated circuits (ICs); design automation; integrated circuit layout;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2006.878475
Filename :
1664908
Link To Document :
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