DocumentCode
1065252
Title
High-speed and low-power feRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme
Author
Zhang, G. ; Jia, Z. ; Ren, T. ; Chen, H.
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing
Volume
45
Issue
12
fYear
2009
Firstpage
610
Lastpage
612
Abstract
A novel design method for nonvolatile ferroelectric random access memory (FeRAM) using a merged bitline (BL)/plateline (PL) array architecture with a twin bitline-driven scheme is proposed. This method is effective in improving the FeRAM performance and reduces the power consumption. A 128 Kbit FeRAM prototype applying the proposed circuitry is implemented. The chip size, access time and memory array power dissipation are reduced to about 87, 44 and 15.8%, respectively, in comparison with those of conventional FeRAM.
Keywords
ferroelectric storage; integrated circuit design; integrated memory circuits; low-power electronics; random-access storage; high-speed FeRAM; low-power FeRAM; memory array power dissipation; merged bitline-plateline array architecture; nonvolatile ferroelectric random access memory; power consumption; storage capacity 128 Kbit; twin bitline-driven scheme; twin-bitline-driven scheme;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2009.0173
Filename
5069767
Link To Document