DocumentCode :
1065267
Title :
Maze routing with buffer insertion under transition time constraints
Author :
Huang, Li-Da ; Lai, Minghorng ; Wong, D.F. ; Gao, Youxin
Author_Institution :
Dept. of Comput. Sci., Univ. of Texas, Austin, TX, USA
Volume :
22
Issue :
1
fYear :
2003
fDate :
1/1/2003 12:00:00 AM
Firstpage :
91
Lastpage :
95
Abstract :
The authors address the problem of simultaneous routing and buffer insertion. Recently the authors considered simultaneous maze routing and buffer insertion under the Elmore delay model. Their algorithms can take into account both routing obstacles and restrictions on buffer locations. It is well known that the Elmore delay is only a first-order approximation of signal delay and hence could be very inaccurate. Moreover, constraints cannot be imposed on the transition times of the output signal waveform at the sink or at the buffers on the route. The authors extend the algorithm in so that accurate delay models (e.g., transmission line model, delay lookup table from SPICE, etc.) can be used. They show that the problem of finding a minimum-delay buffered routing path can be formulated as a shortest path problem in a specially constructed weighted graph. By including only the vertices with qualifying transition times in the graph, they guarantee that all transition time constraints are satisfied. Their algorithm can be easily extended to handle buffer sizing and wire sizing. It can be applied iteratively to improve any given routing tree solution. Experimental results show that their algorithm performs well.
Keywords :
VLSI; circuit layout CAD; delay estimation; graph theory; integrated circuit layout; network routing; accurate delay models; buffer insertion; buffer location restriction; buffer sizing; delay lookup table; maze routing; minimum-delay buffered routing path; routing obstacles; routing tree solution; shortest path problem; signal delay; simultaneous routing/buffer insertion; transition time constraints; transmission line model; weighted graph; wire sizing; Delay lines; Iterative algorithms; Routing; SPICE; Shortest path problem; Table lookup; Time factors; Transmission lines; Tree graphs; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2002.805725
Filename :
1158256
Link To Document :
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