DocumentCode :
1065855
Title :
Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding
Author :
Hsu, Hui-Cheng ; Lee, Kun-Bin ; Chang, Nelson Yen-Chung ; Chang, Tian-Sheuan
Author_Institution :
MediaTek, Inc., Hsinchu
Volume :
18
Issue :
3
fYear :
2008
fDate :
3/1/2008 12:00:00 AM
Firstpage :
375
Lastpage :
386
Abstract :
This paper presents efficient VLSI architectures of the shape-adaptive discrete cosine transform (SA-DCT) and its inverse transform (SA-IDCT) for MPEG-4. Two of the challenges encountered during the exploitation of more efficient architectures for the SA-DCT and SA-IDCT are addressed. One challenge is to handle the architectural irregularity due to the shape-adaptive nature. The other one is to provide acceptable throughput using minimal hardware. In the algorithm-level optimization, this work exploits the numerical properties found in the transform matrices of various lengths, and derives a fine-grained zero-skipping scheme for the IDCT which can perform 22.6% more zero-skipping than the common vector-based coarse-grained zero-skipping scheme does. In the architecture-level design, the 1-D variable-length DCT/IDCT architectures designed on the basis of the numerical properties are proposed. An auto-aligned transpose memory that aligns the data of different lengths is also incorporated. In addition, a zero-index table is also included in the transpose memory to support the fine-grained zero-skipping in the SA-IDCT. The synthesized designs of the SA-DCT and SA-IDCT are implemented using UMC 0.18-mum technology. The SA-DCT architecture has 26 635 gates, and its average cycle-throughput is 0.66 pixels/cycle, which is comparable to other proposed architectures. On the other hand, the SA-IDCT architecture has 29 960 gates, and its cycle-throughput is 6.42 pixels/cycle. While decoding for CIF@30FPS, the SA-IDCT is clocked at 0.7 MHz, and the power consumption is 0.14 mW. Both the throughput and power consumption of the proposed SA-IDCT architecture are an order better than those of the existing SA-IDCT architectures.
Keywords :
VLSI; adaptive codes; data compression; decoding; discrete cosine transforms; matrix algebra; optimisation; transform coding; video coding; MPEG-4 video coding; VLSI architecture; algorithm-level optimization; auto-aligned transpose memory; decoding; inverse transform; power consumption; shape-adaptive discrete cosine transform; transform matrix; zero-index table; zero-skipping scheme; Discrete cosine transform (DCT); MPEG-4; Not given.; VLSI; video coding;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/TCSVT.2008.918275
Filename :
4449077
Link To Document :
بازگشت