Title :
Sub-1-V CMOS proportional-to-absolute temperature references
Author :
Serra-Graells, Francisco ; Huertas, José Luis
Author_Institution :
Comput. Eng. Dept., Univ. Autonoma de Barcelona, Spain
fDate :
1/1/2003 12:00:00 AM
Abstract :
Presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (μA) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-μW integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-μm very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+>60 dB. Hence, the resulting PTAT circuits are suitable for very-low-voltage system-on-a-chip applications in digital CMOS technologies.
Keywords :
CMOS integrated circuits; VLSI; compandors; integrated circuit design; reference circuits; system-on-chip; 0.35 micron; 1.2 micron; CMOS; PSRR; PTAT; design equations; log companding; proportional-to-absolute temperature references; supply scaling; very large scale integration; very-low-voltage system-on-a-chip; weak inversion; Analytical models; CMOS technology; Circuit simulation; Circuit testing; Equations; Integrated circuit technology; MOSFET circuits; Temperature; Threshold voltage; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.806258
