Title :
A new high-performance programmable delay line IC
Author :
Dejhan, K. ; Jutand, F. ; Demassieux, N. ; Colavin, O. ; Galisson, A. ; Artieri, A.
Author_Institution :
Dept. Electron., Ecole Nat. Superieure des Telecommun., Paris, France
fDate :
11/1/1989 12:00:00 AM
Abstract :
A novel implementation of a programmable digital delay line based on a shift register for video applications is presented. An optimized register developed to reduce the power dissipation of the register files is described. A compromise between the power dissipation and area of the circuit is used to obtain high performance. The chip features a 20-MHz operating frequency and 200-mW power dissipation. This chip has been designed with a 1.2-μm CMOS technology
Keywords :
CMOS integrated circuits; delay lines; shift registers; 1.2 micron; 20 MHz; 200 mW; CMOS technology; HF; high-performance programmable delay line IC; picture processing; power dissipation; shift register; video applications; CMOS technology; Circuits; Delay lines; Filters; Frequency; Image converters; Pixel; Power dissipation; Random access memory; Shift registers;
Journal_Title :
Consumer Electronics, IEEE Transactions on
