Noise analysis of low noise, high count rate, PIN diode X-ray detectors

A noise analysis for a planned PIN diode X-ray detector array using CMOS technology explores the affect of allowed device dimensions on attainable energy resolution using a methodology which allows low frequency, process dependent 1/f and 1/f² terms to be explicitly evaluated for arbitrary noise filters. We find that enhancement mode MOSFETs are too noisy for this application while, for peaking times τ_p<1 μs and carefully processed buried channel depletion mode MOSFETs, both 1/f and 1/f² terms are negligible and the classical approaches to minimizing noise (reducing gate lengths and minimizing capacitances) remain valid. A concrete example demonstrates expected performance: namely a ΔE of 53 eV FWHM for a 180 ns τ_p at 300 K using a 0.1 pF detector coupled to a 0.5 μm gate length input transistor