Title :
A GPU Implementation of a MAP Decoder for Synchronization Error Correcting Codes
Author_Institution :
Dept. of Comput., Univ. of Surrey, Guildford, UK
Abstract :
In this paper we present a parallel implementation of a MAP decoder for synchronization error correcting codes. For a modest implementation effort, we demonstrate a considerable decoding speedup, up to two orders of magnitude even on consumer GPUs. This enables the analysis of much larger codes and worse channel conditions than previously possible, and makes applications of such codes feasible for software implementations.
Keywords :
channel coding; error correction codes; graphics processing units; maximum likelihood decoding; GPU implementation; MAP decoder parallel implementation; channel conditions; software implementations; synchronization error correcting codes; Complexity theory; Decoding; Graphics processing units; Instruction sets; Kernel; Synchronization; CUDA; GPU; Insertion-deletion correction; MAP decoder; forward-backward algorithm;
Journal_Title :
Communications Letters, IEEE
DOI :
10.1109/LCOMM.2013.031913.130203
