Scalable Matrix Multiplication With Hybrid CMOS-RSFQ Digital Signal Processor

Author

Kataeva, Irina ; Engseth, Henrik ; Kidiyarova-Shevchenko, Anna

Author_Institution

Chalmers Univ. of Technol., Gothenburg

Volume

17

Issue

2

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

486

Lastpage

489

Abstract

We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm² process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm² process.

Keywords

CMOS memory circuits; cache storage; digital signal processing chips; matrix multiplication; HYPRES; bit rate 2 Gbit/s; cache memory; frequency 24 GHz; hybrid CMOS-RSFQ digital signal processor; memory size 3.7 KByte; scalable matrix multiplication; synchronization block; word length 14 bit; word length 18 bit; word length 5 bit; Algorithm design and analysis; Bandwidth; Clocks; Digital signal processing chips; Digital signal processors; Frequency synchronization; Partitioning algorithms; Process design; Signal design; Signal processing algorithms; DSP; RSFQ; hybrid memory; multiply-accumulate unit;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2007.901451

Filename

4277495