Title :
Charge retention of floating-gate transistors under applied bias conditions
Author_Institution :
Intel Corporation, Santa Clara, CA
fDate :
1/1/1980 12:00:00 AM
Abstract :
The nonvolatile memory-retention characteristics of floating-gate transistors with thin gate oxides are shown to be a strong function of both applied voltages and oxide thickness. Under the assumption that the charge loss mechanism is Fowler-Nordheim tunneling through the thin oxide, an expression is derived which allows the design of floating-gate transistors with optimized retention time.
Keywords :
Acceleration; Capacitance; Design optimization; Electrons; Equations; Nonvolatile memory; Temperature; Testing; Threshold voltage; Tunneling;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1980.19856