DocumentCode
1067686
Title
General algorithms for reduced-adder integer multiplier design
Author
Dempster, A.G. ; Macleod, M.D.
Author_Institution
Westminster Univ., London
Volume
31
Issue
21
fYear
1995
fDate
10/12/1995 12:00:00 AM
Firstpage
1800
Lastpage
1802
Abstract
The problem of reducing the number of adders required to perform shift-and-add multiplication is addressed for hardware and software applications. Algorithms invented for each of these applications are compared and found to have similar performances in general. Improved results are achieved by selecting the best design of the two
Keywords
adders; digital arithmetic; logic design; multiplying circuits; adders reduction; reduced-adder integer multiplier design; shift/add multiplication;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
Filename
475072
Link To Document