Power Reduction of Asynchronous Logic Circuits Using Activity Detection

Asynchronous circuits are well known for their benefits in terms of dynamic power savings because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus, asynchronous circuits need to focus on static-power-consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous activity. Associated to an automatic power regulation, it efficiently reduces the supply voltage and, thus, both energy per operation and leakage currents. The proposed technique has been applied to an asynchronous network-on-chip node and successfully implemented in an ST Microelectronics CMOS 65-nm technology.