DocumentCode :
1067997
Title :
Design and evaluation of ion-implanted CMOS structures
Author :
Motamedi, M.E. ; Tam, Ka-yee ; Steckl, Andrew J.
Author_Institution :
Rensselaer Polytechnic Institute, Troy, NY
Volume :
27
Issue :
3
fYear :
1980
fDate :
3/1/1980 12:00:00 AM
Firstpage :
578
Lastpage :
583
Abstract :
An IC chip intended for the integrated signal readout of PbS-Si heterojunction detectors has been designed using a p-well/ n-substrate CMOS structure, The chip contains integrated and discrete n-MOSFET readout circuits as well as test structures. The chip fabrication used ion implantation for all doping steps, including the p well. The fabricated device profiles show good agreement with the results of a process analysis performed using the SUPREM program. Among the experimental n-MOSFET characteristics measured were: 
µmho, 
cm2/V . s, 
V, and 
/ cm2. eV.
µmho, cm2/V . s, V, and / cm2. eV.Keywords :
CMOS integrated circuits; Chip scale packaging; Circuit testing; Detectors; Doping; Heterojunctions; Integrated circuit testing; Ion implantation; MOSFET circuits; Signal design;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1980.19902
Filename :
1480695
Link To Document :
