DocumentCode :
106819
Title :
A Novel Modeling Approach for System-Level Application Mapping Targeted for Configurable Architecture
Author :
Sabaghian-Bidgoli, Hossein ; Ali Shahabi, Seyed ; Navabi, Zainalabedin
Author_Institution :
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
Volume :
37
Issue :
4
fYear :
2014
fDate :
Fall 2014
Firstpage :
192
Lastpage :
202
Abstract :
Advances in chip fabrication technology and increasing demand for meeting time to market have led to the use of the electronic system-level (ESL) design methodology. An important challenge is to find a proper approach by which a given application can be mapped into a specific target architecture, usually called application mapping. In this paper, an abstract modeling approach based on the colored Petri net (CPN) is proposed to map an arbitrary application into a given target architecture. The mapping is at an abstract level and contains timing information that facilitates high-level design space exploration. A complete stepwise procedure is presented to illustrate how a CPN model of the application is refined and employed to extract the required tasks for a given target architecture. The fact that models obtained as such are executable makes the required performance evaluation and exploration possible, and thus, will result in better architectural decisions at the design stage. The usefulness of the proposed approach is assessed using several alternative mapping schemes of the JPEG encoder. The actual encoding time and the required simulation time indicate the advantages of this method over design-space exploration that would otherwise be done in SystemC, which is the natural choice in today´s ESL designs.
Keywords :
Petri nets; encoding; integrated circuit design; integrated circuit manufacture; integrated circuit modelling; integrated circuit technology; CPN model; ESL design methodology; JPEG encoder; SystemC; abstract modeling approach; chip fabrication technology; colored Petri net; complete stepwise procedure; configurable target architecture; electronic system-level; encoding time; high-level design space exploration; system-level application mapping; timing information; Computational modeling; Computer architecture; Design methodology; Hardware; Mathematical model; Parallel processing; Time-varying systems; Application mapping; colored Petri net (CPN); configurable architecture; design-space exploration; electronic system level (ESL); system-level modeling;
fLanguage :
English
Journal_Title :
Electrical and Computer Engineering, Canadian Journal of
Publisher :
ieee
ISSN :
0840-8688
Type :
jour
DOI :
10.1109/CJECE.2014.2326054
Filename :
6994944
Link To Document :
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