Title :
Techniques to Prioritize Paths for Diagnosis
Author :
Adapa, Rajsekhar ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fDate :
4/1/2010 12:00:00 AM
Abstract :
Existing techniques for path delay fault (PDF) diagnosis prune fault-free candidates using nonfailing patterns but fail to reduce the size of suspect set significantly. This paper presents two alternative techniques that can be applied in a postprocessing manner to further reduce the suspect set by prioritizing paths using only the failing patterns. Experimental results on the ISCAS benchmarks demonstrate that they are time and memory efficient.
Keywords :
failure analysis; fault diagnosis; integrated circuit testing; ISCAS benchmarks; nonfailing patterns; path delay fault diagnosis prune fault-free candidates; postprocessing; suspect set size reduction; Failure analysis; fault diagnosis; path delay faults (PDFs); testing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2013469
