DocumentCode :
1068285
Title :
Optimal  \\Sigma \\Delta Modulator Architectures for Fractional-  {N} Frequency Synthesis
Author :
Sleiman, Sleiman Bou ; Atallah, Jad G. ; Rodriguez, Saul ; Rusu, Ana ; Ismail, Mohammed
Author_Institution :
Analog VLSI Lab., Ohio State Univ., Columbus, OH, USA
Volume :
18
Issue :
2
fYear :
2010
Firstpage :
194
Lastpage :
200
Abstract :
This paper presents a comparative study of ΣΔ modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone´s phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.
Keywords :
frequency synthesizers; phase locked loops; phase noise; sigma-delta modulation; ΣΔ modulator; charge pump current mismatch; fractional-N frequency synthesis; fractional-N phase-locked loops; phase noise; quantization noise; sigma-delta modulators; $ Sigma Delta$ modulation; Frequency synthesizers; phase noise; phase-locked loops (PLLs);
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2008.2009058
Filename :
5071193
Link To Document :
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