Title :
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic
Author :
Ashouei, Maryam ; Chatterjee, Abhijit ; Singh, Adit D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fDate :
4/1/2010 12:00:00 AM
Abstract :
In this paper, an architectural framework for post-silicon tuning of nanoscale CMOS circuits is developed. The tuning methodology is driven by a ??tunable?? gate design that allows the gate to be switched from a high-speed/high-power mode to a low-speed/low-power mode under digital control. A small number of ??critical?? logic gates are replaced with tunable gates for post-silicon power-performance tuning. In addition, supply voltage and body bias can be employed as hardware ??tuning knobs?? as well to deal with delay and leakage variations. After silicon is manufactured, the hardware ??knobs?? are programmed through the use of an implicit self-test methodology that can be exercised by the proposed self-adaptation architectural framework. It is seen that the delay yield can be improved by an average of 40% with minimal impact on area.
Keywords :
CMOS logic circuits; SPICE; automatic testing; circuit tuning; logic design; logic testing; reconfigurable architectures; silicon; Si; body bias; critical logic gates; hardware knobs; hardware tuning knobs; high-speed-high-power mode; implicit delay prediction; leakage variations; low-speed-low-power mode; nanoscale CMOS yield recovery; post-manufacture tuning; post-silicon power-performance tuning; post-silicon tuning; programmed hardware knobs; reconfigurable logic; self-adaptation architectural framework; self-test methodology; supply voltage; tunable gate design; Process variation; reconfiguration; tunable gate; yield improvement;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2014559