0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin

A three-stage amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C_L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain-bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G_m-boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm² of area and 15.8 μW of power, the 0.18 μm CMOS three-stage amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/μs average slew rate and 56.2° PM at 1 nF C_L. Stable responses with >50° PM are attained for a 10 × range of C_L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.