Title :
High performance 3.3- and 5-V 0.5-μm CMOS technology for ASIC´s
Author :
Kizilyalli, Isik C. ; Thoma, Morgan J. ; Lytle, Steve A. ; Martin, Edward P., Jr. ; Singh, Ranbir ; Vitkavage, Susan C. ; Bechtold, Philip F. ; Kearney, Joseph W. ; Rambaud, Marta M. ; Twiford, Michael S. ; Cochran, William T. ; Fenstermaker, Larry R. ; F
Author_Institution :
AT&T Bell Labs., Orlando, FL, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
Process integration of two manufacturable high performance 0.5-μm CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; hot carriers; integrated circuit modelling; integrated circuit reliability; integrated circuit technology; isolation technology; 0.5 micron; 3.3 V; 5.0 V; 80 ps; ASICs; CMOS technology; MOS transistor design; circuit performance sensitivity; gate length control; gate oxide control; hot carrier reliability; poly-buffered LOGOS isolation; power consumption; process fluctuations; ring oscillator delay; speed; statistical modeling; CMOS process; CMOS technology; Circuit optimization; Fluctuations; Hot carriers; Isolation technology; MOSFETs; Manufacturing processes; Semiconductor device modeling; Virtual manufacturing;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
