Title :
A 110-MHz/1-Mb synchronous TagRAM
Author :
Unekawa, Yasuo ; Kobayashi, Tsuguo ; Shirotori, Tsukasa ; Fujimoto, Yukihiro ; Shimazawa, Takayoshi ; Nogami, Kazutaka ; Nakao, Takehiko ; Sawada, Kazuhiro ; Matsui, Masataka ; Sakurai, Takayasu ; Tang, Man Kit ; Huffman, William A.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
fDate :
4/1/1994 12:00:00 AM
Abstract :
A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-μm double polysilicon double-metal BiCMOS technology
Keywords :
BiCMOS integrated circuits; buffer storage; content-addressable storage; integrated memory circuits; random-access storage; 0.7 micron; 1 Mbit; 1.189 Mbit; 110 MHz; 16 Mbyte; 4-way set associative RAM; 9 ns; BiCMOS main decoder; BiCMOS sense-amplifying comparator; PLL; Si; double polysilicon process; double-metal BiCMOS technology; doubly placed self-timed write circuits; highly linear VCO; pipelined decoding scheme; secondary cache system; single PMOS load; synchronous TagRAM; Application software; Bandwidth; BiCMOS integrated circuits; Cache memory; Computer architecture; Decoding; High performance computing; Microelectronics; Microprocessors; System-on-a-chip;
Journal_Title :
Solid-State Circuits, IEEE Journal of
