DocumentCode
1068376
Title
Yield loss mechanisms in MOS-gated power devices
Author
Venkatraman, Prasad ; Baliga, B.Jayant
Author_Institution
Power Products Div., Motorola Inc., Phoenix, AZ, USA
Volume
8
Issue
4
fYear
1995
fDate
11/1/1995 12:00:00 AM
Firstpage
451
Lastpage
453
Abstract
Defects which cause yield loss in MOS-gated power devices are discussed. Design and fabrication of a test element group for analysis of gate to source shorts in MOS-gated power devices are described. Experimental results obtained from these test elements are presented, based upon which it is demonstrated that gate to source shorts in power MOS-gated devices occur mainly along the edge of the polysilicon gate. The contact window opening step has been found to have a strong influence on the density of gate to source shorts
Keywords
circuit optimisation; integrated circuit yield; power semiconductor devices; semiconductor device testing; MOS-gated power devices; contact window opening step; gate to source shorts; polysilicon gate; test element group; yield loss mechanisms; CMOS technology; Cobalt; Electrical resistance measurement; Fabrication; Integrated circuit modeling; Integrated circuit yield; Particle measurements; Semiconductor films; Silicides; Testing;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/66.475189
Filename
475189
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