Title :
16-Mb synchronous DRAM with 125-Mbyte/s data rate
Author :
Choi, Yunho ; Kim, Myungho ; Jang, Hyunsoon ; Kim, Taejin ; Lee, Seung-Hoon ; Lee, Ho-cheol ; Park, Churoo ; Lee, Siyeol ; Kim, Cheol-soo ; Cho, Sooin ; Haq, Ejaz ; Karp, Joel ; Chin, Daeje
Author_Institution :
Samsung Electronics, Kyungki-Do, South Korea
fDate :
4/1/1994 12:00:00 AM
Abstract :
In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M×8) achieves a 125-Mbyte/s data rate using 0.5-μm twin well CMOS technology
Keywords :
CMOS integrated circuits; DRAM chips; memory architecture; 0.5 micron; 125 Mbyte/s; 16 Mbit; DRAM architecture; SDRAM; burst length; burst type; memory bandwidth; programmable latency; synchronous DRAM; twin well CMOS technology; Bandwidth; CMOS technology; Clocks; Costs; Delay; Frequency; Interleaved codes; Pipeline processing; Random access memory; SDRAM;
Journal_Title :
Solid-State Circuits, IEEE Journal of
