Control of gate—Drain avalanche in GaAs MESFET´s

The onset of gate-drain avalanche imposes an important fundamental constraint on the drain voltage swing, and hence, on the output power of GaAs FET\´s. In this paper we show that recognition of the role of surface depletion and proper attention to channel design can yield avalanche voltage factors of 2-3 above bulk values. The appropriate design strategy is minimization of the undepleted epitaxial charge per unit area (Qu) between gate and drain, which, in turn, dictates a gate-notch depth approximately equal to the surface zero-bias depletion depth. A simple lateral spreading model is proposed which predicts that , where VLis the gate-drain avalanche voltage and Quis measured in units of 10¹²electrons/cm². This prediction is supported by a large body of experimental dc and pulse data, although considerable scatter is observed which we have attributed to epi charge nonuniformities, premature avalanche at the rough edges of AI gates formed by a liftoff process, and surface charging variations associated with dielectric passivation. The observed dependence of VLon epi charge rather than on doping level, as predicted for bulk avalanche, provides convincing evidence for nonbulk two-dimensional avalanche in the thin-film ( ) FET geometry. In thick films ( ), on the other hand, it is found that the bulk avalanche predictions are reasonably accurate. In terms of saturated epi current Is, the bulk regime corresponds to mA/mm and the lateral spreading (thin-film) regime to mA/mm. Finally, we have found that gate-drain avalanche is the major cause of output saturation as a function of drain potential in power GaAs FET\´s.