DocumentCode :
1068957
Title :
Planar GaAs MOSFET integrated logic
Author :
Yokoyama, Naoki ; Mimura, Takashi ; Fukuta, Masumi
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Volume :
27
Issue :
6
fYear :
1980
fDate :
6/1/1980 12:00:00 AM
Firstpage :
1124
Lastpage :
1128
Abstract :
Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET´s. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.
Keywords :
Application specific integrated circuits; Digital integrated circuits; Gallium arsenide; Ion implantation; Lithography; Logic devices; MOSFET circuits; Plasma applications; Plasma immersion ion implantation; Propagation delay;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1980.19995
Filename :
1480788
Link To Document :
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