DocumentCode
106906
Title
Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme
Author
Song Jia ; Shilin Yan ; Yuan Wang ; Ganggang Zhang
Author_Institution
Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China
Volume
51
Issue
6
fYear
2015
fDate
3 19 2015
Firstpage
464
Lastpage
465
Abstract
A new design scheme intended to improve the performance of true single-phase clocked (TSPC) dual modulus prescalers is presented. Two branches of TSPC D flip-flops are merged to reduce both power and device count. An HSPICE simulation of the proposed scheme demonstrates the highest power efficiency and best power-delay product among the referenced designs.
Keywords
circuit simulation; flip-flops; high-speed integrated circuits; logic design; logic gates; low-power electronics; HSPICE simulation; TSPC D flip-flops; branch-merged true single-phase clocked scheme; low-power high-speed dual modulus prescalers; power efficiency; power-delay product;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2014.4146
Filename
7062198
Link To Document