• DocumentCode
    1069404
  • Title

    Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

  • Author

    Ohta, Kuniichi ; Yamada, Kunio ; Saitoh, Manzoh ; Shimizu, Kyozo ; Tarui, Yasuo

  • Author_Institution
    I.C. Division, Kawasaki, Japan
  • Volume
    27
  • Issue
    8
  • fYear
    1980
  • fDate
    8/1/1980 12:00:00 AM
  • Firstpage
    1352
  • Lastpage
    1358
  • Abstract
    A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm2/cell, namely 3 × 2 mm2/1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)
  • Keywords
    Anisotropic magnetoresistance; Capacitance; Etching; Integrated circuit interconnections; Ion implantation; Laboratories; MOSFET circuits; Process design; Registers; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1980.20039
  • Filename
    1480832