Title :
Fast parallel algorithm for ternary multiplication using multivalued I2L technology
Author :
De, Mallika ; Sinha, Bhabani P.
Author_Institution :
Univ. Sci. Instrum. Centre, Kalyani Univ., India
fDate :
5/1/1994 12:00:00 AM
Abstract :
Presents an algorithm for parallel multiplication of two n-bit ternary numbers. This algorithm uses the technique of column compression and computes the product in (2 upper bound [log2n]+2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers
Keywords :
digital arithmetic; parallel algorithms; systolic arrays; ternary logic; balanced ternary logic; column compression; negative numbers; parallel algorithm; parallel multiplication; precarry addition; single-bit ternary full adder; systolic architecture; ternary multiplication; Adders; Computer architecture; Concurrent computing; Delay; Integrated circuit interconnections; Iterative algorithms; Logic gates; Multivalued logic; Parallel algorithms; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
