Title :
Test pattern generation for circuits with tri-state modules by Z-algorithm
Author :
Itazaki, Noriyoshi ; Kinoshita, Kozo
Author_Institution :
Dept. of Inf. Sci., Hiroshima Univ., Japan
fDate :
12/1/1989 12:00:00 AM
Abstract :
An algorithmic test pattern generation method named ZALG* for circuits including tri-state modules that have been extensively used in recent MOS VLSI is presented. For the circuits, special attention must be paid to bus clash and memory retention in order to avoid device destruction in testing. Since ZALG* takes complete measures against bus clash and memory retention and uses a multiple-path sensitization method, like PODEM, it is a complete algorithm in the sense that all possible combinations of input values will be tried in the worst case. ZALG* is implemented by FORTRAN, and some experimental results for circuits with two to three thousand gates are reported
Keywords :
MOS integrated circuits; VLSI; integrated circuit testing; integrated logic circuits; logic testing; ternary logic; FORTRAN; MOS VLSI; PODEM; Z-algorithm; ZALG*; algorithmic test pattern generation method; bus clash; logic IC testing; memory retention; multiple-path sensitization method; tri-state modules; tristate logic; Art; Circuit faults; Circuit testing; Clocks; Computational efficiency; Fault detection; Fault tolerance; Integrated circuit testing; Test pattern generators; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
